The integration of copper into semiconductor processing presents new opportunities – and challenges.

To satisfy the increasing demand for faster signal transport by the computing and telecommunication industries, copper thin film and low capacitance materials are becoming vital for high performance circuits of the future. Copper has lower electrical resistance and superior resistance to electromigration compared to aluminum and is in the process of replacing aluminum as the interconnect metal for the next generation of integrated circuits. The combination of copper with low-k materials promises to provide better driving speed, improved noise tolerance, and low power dissipation required for the next generation of ASIC and logic devices.

Such integration, however, still faces a number of challenges associated with material properties and subsequent processing (dual damascene) to achieve high throughput with increased yield. One such yield related challenge is to control the copper contamination of the front-end-of-line (FEOL) processes. Copper is used at back-end-of-line (BEOL) processes for interconnect metallization and can cause cross-contamination to FEOL applications.

Additional risks of such contamination also exist for non-copper BEOL processes. In this article, we discuss measures for minimizing and/or eliminating the copper contamination from the work and processes associated with the cleanroom environment. Though various sources of contamination by copper exist, particular emphasis is placed on the prevention of contamination using the principle of segregation. Identification of contamination sources and an understanding of the risk of copper contamination is key to the successful implementation of procedures to control and prevent such contamination to FEOL and non-copper BEOL processes.

Consequence of Copper Contamination

Considerable effort has been made in recent years to evaluate the detrimental effect of metals including copper, on the integrity of thin gate oxide in FEOL application. Metallic contamination of the silicon surfaces results in device defects and subsequent yield loss.¹ Higher tunneling current, lower charge-to-breakdown characteristics, and worse, stress induced leakage current are observed even at low copper contamination levels. This is suggested to be due to precipitation of copper salicide in both oxide as well as silicon-oxide interfaces which further reduces the effective thickness of the oxide layer and induces higher tunneling current.²