In CMOS integrated circuits the lateral NPN (LNPN) bipolar transistor parasitic to the NMOSFET output buffer has historically served as the dominant ESD clamping device [1-3]. However, as process technologies have scaled below 0.25µm design rules, the LNPN device has become increasingly fragile, process sensitive, and less suitable for use in ESD protection [4-5]. Clearly a more robust, scalable, and process portable ESD clamping solution is needed.

An attractive alternative to the LNPN clamp is the transient triggered active MOSFET rail clamp [6-11]. Figure 1 illustrates a schematic of a typical clamp circuit for ESD protection. The clamp circuit consists of a simple resistor-capacitor transient detector (R1-C1), a buffer circuit, and a large NMOS transistor (M1). M1 acts as the primary clamping device in the circuit relying only on MOSFET action to dissipate current during an ESD event.

In Figure 2, we show an example schematic to demonstrate the use of active MOSFET rail clamps for I/O pad ESD protection. In addition to the NMOS and PMOS buffer transistors, we also show various elements parasitic to these devices. The two intended paths for the I/O positive to VSS ESD event are shown with gray arrows in Figure 2. Both paths utilize the PMOS transistor's parasitic vertical PNP (VPNP) bipolar junction transistor formed by the p+ source/drain region, the VDD nwell, and substrate VSS [13-18]. The majority of the ESD current follows Path 1 to VSS, via the forward biased emitter/base junction of the VPNP, then to the VDD rail, and from there through the active MOSFET rail clamp. A portion of the ESD current follows Path 2, directly from the I/O to VSS via the collector of the VPNP.

Active MOSFET rail clamps enjoy numerous advantages over traditional parasitic LNPN-based clamps. Relying only on MOSFET action, they are much less process sensitive, and therefore, unlike LNPN-based ESD networks, easily ported across wafer fabs. With the active MOSFET rail clamp approach, the ESD optimization emphasis is shifted from process to circuit design allowing use of standard circuit simulation tools like SPICE to develop and port robust ESD protection solutions for multiple fabs and processes.

Still, there are some clear disadvantages of active MOSFET networks. The first is layout area. Two or more rail clamps the size of an on-chip wire bond pad are often needed to dissipate the required ESD current. In addition, to achieve the required on-time (~1000ns), the trigger circuit may occupy 20-40% of the total rail clamp area. Since these rail clamp circuits are quite large, they are typically placed in power and ground pad cells or, where possible, in large spacer cells between pads. In many chip applications, large banks of tightly packed I/O pads must be placed, offering no room for large ESD rail clamp circuits and thus, decreasing I/O ESD performance due to increased distance of center I/Os from the remote rail clamps. In these "pad-limited" designs the VDD and VSS bus resistance (RVDD and RVSS in Figure 2) between the I/O pad and the active MOSFET rail clamp plays a critical role in the resulting ESD robustness. Assuming, for example, a peak ESD current of 3.8A, an I/O to clamp bus resistance of 2 ohms will impart a 7.6V added potential drop in the ESD path. This may be impossible to overcome with increased rail clamp MOSFET width or VPNP perimeter. This dependence on bus resistance is the second disadvantage of the typical MOSFET-based ESD network.

In this paper, we introduce a new, highly efficient distributed active MOSFET rail clamp network which overcomes these disadvantages. We demonstrate our network design methodology utilizing data from a fully silicided, sub-0.25µm, dual gate oxide, retrograde nwell, bulk CMOS technology. In this new network, rail clamp NMOS transistors are distributed in each I/O pad cell, while the primary clamp triggering elements remain remotely placed in power and ground pad cells. We will show that this approach offers surprising advantages in ESD performance, layout area efficiency, bus resistance tolerance, and I/O ring design flexibility.

Distributed Rail Clamp Networks

To significantly reduce the effect of bus resistance, we have developed a new distributed ESD network in which small rail clamp circuits are placed in each I/O pad cell. As our network analysis results will show, this is a very effective means to provide robust, uniform ESD protection to all I/O pads, independent of location in the pad ring.

One challenge to developing this network was the constraint of limited available area, particularly in the crowded I/O pad cell. While the primary rail clamp NMOS transistor (M1 in Figure 1) can easily be downsized for placement in a distributed network of smaller clamps, the trigger circuit, unfortunately, cannot be similarly scaled and would be impractical to place in the I/O pad cell.

Our solution to this problem was to distribute an array of smaller rail clamp NMOS transistors in each I/O pad cell, while placing the primary RC trigger in remote locations, like the power and ground pad cells [19]. This new approach is illustrated in Figure 3.

NMOS transistor, capacitor, and buffer circuit while the primary trigger circuit and large NMOS clamps are placed in the power pads.

A small NMOS transistor, a buffer circuit, and a small capacitor is placed in each I/O pad cell. In each power or ground pad cell a complete large rail clamp circuit as in Figure 1 is placed. A key feature of this approach is that we tap the output of the RC trigger in each of the power pad cells and route this output (ESD_RC) via a narrow metal bus to the small clamps in each I/O pad cell. Note that both the small capacitors (C2), placed in each I/O pad cell, and the ESD_RC bus resistance, supplement the remote large capacitor C1 and resistor R1 in the distributed rail clamp operation. There is no delayed turn-on of the distributed clamps since, for positive VDD to VSS zaps, each clamp is triggered on locally, by capacitors C1 or C2. The time-out function, on the other hand, is controlled remotely, via the resistor R1. For this reason, we can tolerate a narrow, somewhat resistive ESD_RC bus.

A simple conceptual schematic of a pad group utilizing such a distributed rail clamp network is shown in Figure 4. The schematic is divided into seven regions corresponding to five I/O pad cells and VDD and VSS power pad cells. The incremental (pad-to-pad) VDD bus resistance (rvdd) and VSS bus resistance (rvss) are shown between each pad. Each I/O pad cell contains the small rail clamp circuit from Figure 3, as well as the VPNP and the substrate return diode from Figure 2. The large clamp circuit from Figure 3 may be seen in the VDD and VSS pad cells. A key feature of the distributed approach is that for any stressed pad in a bank of I/Os, the ESD burden does not fall only on the small clamp local to the stressed pad. This local clamp, plus its neighbors on each side, work in parallel to safely dissipate the ESD current. The gray arrows in Figure 4 demonstrate the single VPNP path plus multiple rail clamp paths to VSS for an ESD pulse applied to the center I/O pad. Due to this distributed protection, the clamps in each I/O may be sized quite small, minimizing the layout area impact.

It turns out that the distributed network shown in Figure 4 offers significant advantages in ESD performance and design flexibility.

Network Simulation with SPICE

A primary advantage of active MOSFET-based ESD protection is the ability to perform network simulation with standard SPICE tools. Our first goal was to assemble a SPICE-based representation of an ESD network like that shown in Figure 4. To perform accurate network simulations one needs to gather the following:

* Compact models for all active devices valid into the high-current ESD regime.

* SPICE subcircuits to define the required ESD stress events the network must tolerate.

* Realistic failure constraints to define when and where damage occurs in the network. These failure thresholds should be extracted from measurements of actual structures on silicon.

* A netlist describing the full network, with each active device and all relevant interconnect resistances included. Ideally the resistances should be back-annotated to the netlist based on a post-layout extraction.

Compact Models

We found that our standard internal compact model deck for the technology was very accurate in predicting MOSFET behavior, even under the moderately elevated bias conditions the rail clamps see during ESD. However, in order to correlate measured and simulated results, we found it critical to include carefully extracted interconnect resistances from the test structures. For the VPNP, we found it necessary to create a new VPNP model in order to get good correlation in the high current regime. To create our new model, two extensions were made to the SGP model available in VerilogA [23]. Details of our model can be found in [26].

ESD Stress Definition

We typically design our rail clamp networks so that the chip may survive a 200V Machine Model (MM) ESD event, but other levels of performance can be targeted as required. We built a SPICE subcircuit for a MM source similar to one previously reported [24]. The circuit produces a peak current of about 3.8A, when pre-charged to 200V.

Simulation Failure Constraints

For all simulations presented here, we assumed that the ESD failures only occur in the rail clamp NMOS or in the NMOS pull-down output buffer connected to the zapped I/O pad since our experience has shown these failures are by far the most common with active MOSFET rail clamp networks. The purpose of the SPICE simulation was then to ensure that the protection network prevented the circuit from reaching either of these two defined failure thresholds.

For all our simulations, we set a limit on the maximum local clamp current, ICLAMP < 1.2mA/µm. This allows a reasonable margin to the true failure threshold which is shown in Figure 5. Failure in the clamp occurs due to LNPN bipolar turn-on.

As shown in Figure 6, the Vt1 of the NMOSFET pull-down output buffer may range from 7.9V, for the single NMOSFET case, up to 11.6V, depending on the choice of cascoded buffer configuration [12]. It should be pointed out that all of these structures suffered immediate permanent thermal damage upon the transition into bipolar conduction. For this reason, we must prevent the LNPN parasitic to the I/O output buffer from ever participating in an ESD event. During an I/O to VSS event, the protection network must dissipate the full ESD current while holding the potential difference across the NMOS output buffer to less than Vt1. We define this potential difference between the zapped I/O and the VSS bus local to that pad with the term VBUFFER. For all simulations presented here, we assume failure occurs whenever VBUFFER > 7V. Higher or lower failure thresholds may be defined as needed. Note that this constraint provides some margin even for the most sensitive single NMOS output buffer configuration.

Description of the Network Netlist

All the simulation results which follow utilize a network similar to that described in Figure 4, except that the number of I/O pads was varied as needed. Unless indicated otherwise, each I/O bank simulated was always terminated with a VSS pad on one end and a VDD pad on the other, just like in Figure 4. We will show that the large rail clamp in these power pads was essential to properly terminate a bank of distributed small rail clamps in the I/O pads. This termination was necessary to insure that the I/O pads near the ends of a large bank exhibit comparable ESD performance to those pads in the center of the bank.

For all simulations, the ESD stressing was limited to the single case of I/O pad zaps positive to VSS grounded. However, the stress event could be applied to any I/O pad in the bank. In addition, the ESD source ground point could be applied at any point on the VSS bus. While this is somewhat unrealistic for actual chip stressing, it was the most useful for network optimization purposes because it provides the highest stress across the fragile NMOS output buffer.

Comparison of Remote and Distributed Clamp Network Performance

Before focusing on how to optimize ESD device sizes in distributed rail clamp networks, we first provide an example to demonstrate the superiority of this approach over the remote rail clamp approach. Netlists for two 21 I/O pad groups were assembled. A simple drawing of a 21 I/O pad bank is shown in Figure 7.

One pad group utilizes remote large rail clamp circuits placed only in the power pads at the ends of the I/O bank. The second pad group features our distributed rail clamp network, with optimized sizings for the ESD devices. For both pad groups the total clamp NMOS transistor width across all 23 pads was kept fixed at Wtotal = 8000µm. For the remote rail clamp network, large MOSFET rail clamp circuits (NMOS W = 4000µm) were placed in the power supply pads on each end of the pad grouping. The I/O pads contain the VPNP bipolar transistors, but no rail clamps. For the distributed network, each of the 21 I/O pad cells contain a small rail clamp circuit (NMOS W = 186µm) in addition to the VPNP, while the power pads on each end of the bank contain a large rail clamp circuit (NMOS W = 2047µm). For both networks, rvdd = 0.2 ohms and rvss = 0 ohms.

Figure 8 shows the simulated peak I/O pad voltage (VBUFFER) for a 200V Machine Model positive ESD event applied I/O to VSS for each I/O pad in both networks. For the network with remote rail clamps, VBUFFER clearly increases with increasing distance from rail clamps in the power supply pads. The center I/O pad (I/O 11) suffers the highest voltage, 8.7V, while the I/Os closest to the VDD and VSS pads see only 6.9V. Recall this variability in VBUFFER is a primary disadvantage of remotely placed MOSFET rail clamp networks. The size of the large clamps and/or the bus resistance must be significantly changed to reduce VBUFFER < 7V. In fact, for these bus resistance values, the two remote rail clamp NMOS transistors must each be increased 35X in width to achieve the 7V criteria for the worst case I/O 11.

The distributed network, on the other hand, exhibits optimum VBUFFER = 7V ESD performance for every I/O pad in the bank. This indicates very efficient utilization of the total available clamp width. From Figure 8, it is clear that the distributed rail clamp network can provide optimum protection to all I/O pads in the bank by utilizing the total network rail clamp width in the most efficient manner possible. The remote clamp network, in contrast, is always limited in performance by bus resistance.

In Figure 9, we show how the ESD current was distributed through each rail clamp in the pad group for an ESD pulse applied to the center pad (I/O 11). The clamp in I/O 11 sees a peak current density of 0.75mA/µm, which is well below our 1.2mA/µm limit. Thus, the rail clamp NMOSFETs are not at risk. A significant portion of the ESD current is also shunted to VSS via the collector of the VPNP bipolar transistor local to the zapped I/O pad [26]. This significantly reduces the load on the MOSFET rail clamp network.