How a network of small rail clamps distributed in every I/O pad cell offers significant advantages in ESD performance as comparedto large, remotely placed rail clamp circuits.

Optimization of Distributed Rail Clamp Networks

Part I, now that we have shown the efficiency of In the distributed approach, in this section we show how to optimally size each of the ESD devices to achieve the target ESD performance. For our optimizations, we use a Motorola internal software tool called MICO [25]. Similar optimization tools are also available commercially. Working in concert with SPICE MICO seeks the local minimum of a user-defined target function by iteratively varying sensitive design parameters, feeding them to the simulator, and sensing their impact on the target.

Sizing the 1/0 Pad ESD Elements

The first set of optimizations determine the minimum perimeter of the VPNP and the minimum width of the small rail clamp NMOSFET in the I/O pads such that the two devices occupy a minimum combined layout area. The optimizations were constrained by the requirements that for a 3.8A peak ESD current, VBUFFER for an I/O pad zapped positive to local grounded VSS must not exceed 7V, and ICLAMP must not exceedl.2mNpm at any point in the network. Grounding the local VSS places the ESD stress directly across the output buffer NMOS devices. During the optimizations, the VPNP and NMOS sizes for all the I/O pads were adjusted simultaneously. Optimizations were repeated for every rvdd and rvss bus resistance value of interest. We ran optimizations for rvdd values ranging from 0.05Q to 0.5Q, at three different rvss values, on, 0.2Q, and 0.4Q.

In our ESD network design, the large rail clamps are only needed to terminate a bank of distributed small rail clamps. Therefore, the I/O pad ESD devices should be sized so that in the center of a very large I/O bank, the distributed small clamps provide full protection, with no assistance from the distant large clamps. To reproduce these conditions, we optimized the I/O pad ESP device sizes for zaps to the center pad in unter minated I/O banks of varying size. An unterminated I/O pad bank contains no large rail clamps at the end of the bank. As the number of I/O pads in the bank increases, the optimum device sizes approach fixed values which are the target sizes for the I/O pad ESD devices.

In Figure 18, the optimum small rail clamp NMOS width and VPNP perimeter for the center I/O pad in an unterminated I/O bank is plotted as a function of the number of I/Os placed in that bank. Only data for the low bus resistance

case, rvdd = 0.05.0. and rySS = 0.0., and the high bus resistance case, rvdd = 0.5.0. and rvss = 0.4.0., are shown.

It is obvious from Figure 18 that for small numbers of I/O pads in a bank, the required VPNP perimeter and NMOS width are very high. In fact, for the single I/O pad case, the optimum device sizes are seen to reduce and eventually saturate.

It is also very clear from Figure 18 that the optimum VPNP and NMOS sizes, after saturation, from the high bus resistance networks are much larger that the optimum sizes from the low bus resistance networks.

The NMOS data in Figure 18 can be explained as follows. For the low bus resistance case, a large number of rail clamps around the zapped I/O may strongly participate in dissipating ESD current. Therefore, as more I/O pads are added to the I/O bank, the optimum NMOS width required is incrementally reduced. In the high bus resistance case, the ESD current is much more constrained to the clamps nearest the zapped I/O. Therefore the optimum NMOS width required saturates more quickly to a much higher final value than in the low bus resistance case.

The VPNP perimeter data in Figure 18 exhibit characteristics similar to the NMOS data, except that the saturation effect occurs sooner. This is because the ESD path utilizes only a single VPNP but multiple small rail ~lamp NMOSFETs. An increase in the NMOS width will therefore provide more ESD performance benefit per unit of layout area. This is the reason the VPNP perimeter data saturates more quickly than the NMOS width data.

From Figure 18, we decided that an unterminated I/O bank of 61 pads should be adequate to extract the optimum VPNP perimeter and small rail clamp NMOS width, even for the lowest bus resistance case.

We calculated the optimum I/O pad ESD device sizes for the center I/O in the unterminated 61 I/O pad bank, for the full range of bus resistance values. The plots in Figures 19 and 20 summarize the relevant information for sizing the I/O pad ESD components in distributed rail clamp networks. Recall that for a given pair of bus resistance values, these device sizes are fixed independent of the number of I/O pads placed in the bank.

Sizing the Large Rail Clamp NMOSFET

A second set of optimizations were run to determine the minimum width of the large rail clamp NMOSFET at both ends of an VO bank to effectively terminate fie network of distributed clamps. We optimize the large rail clamp NMOS width based on zaps applied to a single I/O pad terminated on- both sides with large rail clamp circuits. The WNP perimeter and small rail clamp NMOS width in the I/O pad were fixed at the values determined from the previous optimizations.

Using this procedure, we calculated the optimum large rail clamp NMOS width for the full range of bus resistance values. In Figure 21, the optimum width is plotted as a function of rvdd for the three different rvss values.

We found that large rail clamp circuits, sized as shown in Figure 21, provided effective termination for distributed networks of small rail clamps. This was true for any number of small rail clamps (I/Opads) in the network, and all simulated bus resistance values. In order to demonstrate the role that the large rail clamps play in terminating the distributed network of small clamps, we generated data to compare the ESD performance of a large VO bank, with and without the terminating large rail clamps. Figure 22 shows the simulated peak Vbuffer for a 200V Machine Model zap applied to each I/O pad in an rvdd = O S Q and rmS= 0.4Q network. Two curves are shown, corresponding to the optimized small rail clamp network with and without the large rail clamps for termination. For the unterminated network, while the center I/O pads exhibit optimum ESD performance, the performance clearly degrades at the ends of the I/O bank. With the addition of the terminating large rail clamps, however, optimum performance is achieved for all the I/O pads in the bank.

Discussion Up to this point, our activities have focused on optimizing distributed ESD protection in isolated I/O pad banks, of varying size and bus resistance values. We required that VDD and VSS pads, containing large rail clamps, always be placed on the ends of these banks in order to properly terminate the distributed rail clamp network. Obviously any real chip will feature multiple I/O banks, of varying size, with power and ground pads mixed in among them. In addition, the chip I/O ring may contain only one or perhaps multiple independent VDD and VSS rail segments. How should the distributed rail clamp network approach be implement- ed in these real chip applications? The only restriction with the distributed clamp network is that large clamp circuits must be placed at each end of any protected bus segment. For a chip with continuous, unbroken VDD and VSS supply rings, no large clamp circuits may even be required. In this case the large rail clamp NMOSFET in the power pads may be reduced to the same size as in the I/O pads. However, the power pads would still need the primary RC trigger cir- cuit shown in Figure 3 (see Part I). A wide range of effec- tive ESD protection scenarios, utilizing distributed small rail clamps with large rail clamps for bus segment termina- tion, can be envisioned.

The most appealing feature of our approach is that the modularity of the design makes it feasible to develop an ESD-robust library of I/O and power pad cells that can be used in multiple chip designs. Optimum,ESD performance may be achieved with almost any arrangement of pads. No special ESD design expertise is needed on the part of the pad ring designer. This pad cell library approach allows effective reuse, saves time and money, and reduces risk.

Circuit Level Verification Using the distributed active MOSFET rail clamp approach described here, > 3000V Human Body Model and > 250V Machine Model ESD performance has been achieved in every sub 0.25mm chip design tested. We are waiting for sil- icon on more parts and plan to report more data on products using these networks in the future.

Conclusions In this work, we have demonstrated that our network of small rail clamps distributed in every I/O pad cell in a pad group offers significant advantages in ESD performance as com- pared to prior approaches with large, remotely placed rail clamp circuits. Through simulation, we have shown that the distributed approach makes it possible to size the ESD devices in the network such that every I/O pad in a bank, regardless of its location, can achieve equal ESD performance, under worst case zap conditions. This allows us to make truly efficient use of all available clamp width in our ESD protection networks.

We have demonstrated that a simple methodology for optimizing ESD device sizes can be applied such that the target ESD performance can be achieved in minimum lay out area while still allowing flexibility in pad ring design. This flexibility makes it possible to design ESD- robust I/O and power pad libraries that perform well across a wide range of chip applications.

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