This paper discusses the incorporation of a copper/low-K research and development line into an existing high volume production facility. The main goal of the project was to accomplish the advanced materials (including Cu and Low K) start-up with a minimal budget. This included the relocation and start-up of the R&D tool set in an existing manufacturing facility. Due to the divergent methodologies between R&D and Manufacturing, a significant portion of the planning involved defining the protocols that would be used to safely integrate the two functions. The components of the project included identification of copper equipment for dedicating and sharing, equipment protocol, general housekeeping, clean room attire, wafer handling, copper monitor and containment in the fab, and last but not least, training for all personnel. The project team was comprised of Industrial Engineering, Automation, Process Module Development, Equipment Engineering, Facilities Engineering, Quality Control, Process, and Contamination Control. Preserving R&D flexibility while minimizing contamination risk to the production line was the key focus of the activities.

Discussion

Based on economic conditions of the downturn of 2001, the decision was made to consolidate and relocate LSI Logic’s Santa Clara R&D facility and the development copper backend line to the Gresham, Oregon manufacturing facility. The Gresham fab is a Class 1000 (ISO Class 6) standard mechanical interfaced (SMIFed) (ISO Class 2 minienvironments) 200mm volume application specific integrated circuit (ASIC) production line. The initial decision to relocate the copper backend to Gresham immediately mobilized a team that included industrial, automation, integration, equipment, facilities, process, and contamination control engineers. The first objective was to define the strategy for how the copper process, which is known to be a yield-damaging contaminant in a non-copper fab environment, was to be integrated into the fab.

Based on the current mode of operation of the fab and the limited space available, tools would have to be spread throughout the fab and could not be isolated as is done in most new fabs where a copper process is run. Copper processing is usually done in a confined area with complete separation from front end processing. Three strategies were developed that were defined by the tool locations.

The first strategy was to fully SMIF the tool and locate it in the production cleanroom along side non-copper tools. The second strategy was for tools to be installed in a separate room to be constructed at the end of an existing process area. This room would be designed with a 100% ULPA-filtered ceiling and full open cassette with no SMIF hardware. The third strategy directed that the tools be installed in a separate fab area in a bay and chase fab configuration. Wafers in this area would be removed from the SMIF pod and placed into the tool under a localized minienvironment. Details of these strategies will be discussed later.

After the three processing strategies were defined, a process called “walk the wafer” was carried out to specifically define every step of the procedures that would be used during wafer processing. This included wafer movement, factory software systems, and location and use of the factory automation auto ID system for lot identification. The greatest challenge facing the team was computer integrated manufacturing (CIM) integration. The current method of operation in the wafer fab is by the use of automated equipment interfaces (EIs) for communicating equipment recipes and lot tracking. Based on the three different operational strategies that would be employed, the implementation of EIs would not be easy. A unique EI method would need to be developed for each piece of equipment that was to be run in a non-standard mode (i.e. open cassette).

Wafer Processing Strategies

Three basic strategies for running the copper line would be utilized. Some tools would be upgraded to work within a SMIFed production environment and would at times be shared with the production group. The second tool category was for full-time R&D tools that are “open-cassette” and would be segregated in dedicated R&D rooms. The third category of tools would be open-cassette but would be located in/near SMIF areas.

The goal in the development of these strategies was to minimize or eliminate the potential risk of contamination to the existing fab line while keeping the budget as low as possible. The key directive of this program was that the copper R&D line would be incorporated at the lowest cost. There was no intention of redesigning/upgrading the majority of the R&D tools to be fully SMIFed and automated. Most of the tools that would be transferred were originally configured for an open-cassette environment and were not purchased with EI or SMIF automation upgrade capabilities.

A key component for the successful integration of the copper R&D tools into the production areas was the mechanical and software POD lockout strategy developed by the LSI-Gresham automation group. This protocol would play a key role in the prevention of cross contamination of copper wafers to non-copper wafer tools.

The first strategy was to install the specific tool into the existing production ballroom. This required that the tool be fully SMIFed. It is not necessary, given the budget constraints imposed, that the tools being installed utilizing the strategy one scenario be fully automated and integrated to the EI. There needs to be minimal interface between the EI and the tool such that the factory automation systems maintain that the lot sequencing and test wafers are at the correct step. The tools being installed under this scenario may not be configured with the proper communication software to fully integrate the EI to the level of automation that would be desirable. As a result, certain tools may require manual load and unload by push button vs. automatic starting by the EI.

A plan is in place to eventually have all tools in the main ballroom configured with the same level of EI functionality. Lot verification will however be kept in check utilizing the auto ID system and FactoryWorks. This will require some level of human interaction to verify that the wafers are at the correct step to prevent mis-processing and cross contamination. The POD lock out method will also come into play at this point to ensure a non-copper pod is not attempted to be to run on the tool and a copper pod is not run on a non-copper tool. Figure 1 depicts the mechanical POD lock out method that was developed to protect tools against the possibility of copper contaminated wafers coming in contact with a non-copper tool process.

The basic hardware lockout method is accomplished by the use of different pin sizes incorporated onto to the SMIF port plates. All pod bottoms have been configured with two pins of varying sizes: the first is non-copper; the second is copper clean (wafers that have been backside and bevel cleaned) or copper dirty (wafers where potential Cu contamination exists on the backsides and bevels). This strategy allows for only the correct configuration of pod bottom to be placed on a similarly configured SMIF port plate. Pins were placed on the pod port plates that need to match the hole configuration on the SMIF pod bottom. This fail-safe physical lockout method has proved successful to date in preventing accidental cross contamination.

The second strategy employed in the incorporation of the copper tool set into the existing factory was to design and construct a new “copper only” room in an area of the existing fab. This is a logical choice for the wet process copper tools due to the proximity of the area to the services that would be necessary to service the copper tools. This room would be an open cassette area where the tools would be installed in a bay-chase environment. This room will be referred to as the copper room. The current class of the room is Class 100 (ISO Class 5). Due to the isolation and low traffic area in this room, recent data shows that the room is consistently at a Class 10 or better in particle performance.

The wafers are introduced to the room interface via the automated material handing system (AMHS). The wafers are removed from their pods by a sorter mounted through the wall of the existing fab area. Prior to entering the room, the cassette of wafers are placed in run boxes at a workstation in the room. All the tools installed in this area have the standard vendor installed wafer handling environments. The wafer cassette ID is removed from the run box and placed onto the tool load station cassette port plate. All cassette ports were configured with auto ID units so that the wafers could be identified by the auto ID pill located in the cassette to ensure that they were at the correct processing step. The tools in this room will be run in a manual mode where the operator loads the cassette from the run box onto the tool and pushes the tool start button.

Strategy three was implemented in the expansion portion of the fab facility. This fab area is constructed utilizing the bay and chase concept with the bay area rated at Class 1000 and all tools being partially SMIFed. Similar to the protocol in the copper room, the tools in the fab expansion area will have open minienvironments installed that cover a large enough area in front of the tool so that a work area will exist under the minienvironment. The pod with cassette will be delivered to the minienvironment work area. A “pod-cracking” tool will then open the pod, and the cassette manually removed and placed onto the tools cassette station. These tools will be interfaced to the factory automation systems in a similar manner as the tools in the copper room. All cassette ports are configured with an auto ID unit to maintain lot integrity and verify the status during processing.

Protocols

In addition to the hardware (pod-pins) and software protections for isolating the Cu processes, operating protocols were implemented to protect from cross-contamination. Visual identification cues were implemented. All items that identified “Cu” were blue. This included: cleanroom garments; gloves; signs; hand-tool identification labels; maintenance safety barriers; and visual workplace tape.

The protocols were developed according to each of the three scenarios listed above and are based on current industry available knowledge, coupled with the experience of the development and contamination control engineers. The potential damage from Cu contamination is dependent upon many factors: wafer type; stage of the process; duration of the contaminant presence; and concentration of the Cu. Baseline tests were performed to determine the current level of Cu contamination in the cleanroom prior to the introduction of Cu processing equipment. Cu is already present in the electrical wiring in the tools, in general cleanroom contamination (aka: dirt), and in small amounts in the aluminum used in our current interconnects.

Protocols were broken down into different categories: General cleanroom practices; Gowning; Tool/Material move-in procedures; Cleanliness verification.

The practices varied based upon the room scenario where they were taking place and the nature of the action being performed. General Cu cleanroom protocols addressed issues such as: converting shared tools from Cu use to normal production; cleaning procedures in case a contamination event has occurred (i.e. broken wafer, etc.); methods for handling Cu boxes and pods; open cassette procedures; etc.

Gowning procedures varied upon the location and the type of action taking place. Blue garments are required for any procedure which may result in contact with Cu residue.

Tool/Material move-in procedures are based on the presence or absence of Cu. If it is present, blue gowns, blue gloves, and blue-marked tools are required.

Cleanliness verification protocols deal with the operation and data interpretation of the total X-Ray reflective fluorescence (TXRF) metrology tool in conjunction with test wafers that pass through the wafer handling/processing areas of the equipment. All shared tools must be verified “clean” post Cu operations before they can be returned to production use (Figure 2).

After identifying the critical protocols and the areas where they would be in force, the next task was to develop a training course for all employees on-site including outside contractors. All employees were required to attend the training and pass a test regarding the new procedures and requirements of integrating copper into the facility. Over the course of several weeks every employee attended copper protocol training. The contents of the course included the hazards of copper contamination, gowning requirements, general cleanroom practices, and the associated protocols regarding what can and cannot be done when working with copper contaminated product or materials.

Tool Sharing

In certain cases, due to capacity and equipment related constraints, tool sharing has been enacted for both copper contaminated wafers and non-copper processes. When a tool has been designated to be used for copper contaminated wafer processing, strict protocols are put into place to insure that when the tool is returned to non-copper contaminated wafers, the tool is contamination free. In all cases, after processing wafers that have been exposed to copper contaminated wafers, the tool parts that may have been exposed to copper are wiped down with 90% IPA/10% DI water. After the parts have been cleaned, gettering wafers are run through the tool. The last gettering wafer is then evaluated with TXRF to check for the level of residual Cu on the wafer. The tool is not allowed back into production unless the Cu level is less than 1Xe11 atoms/cm2. In some cases, we have found from testing that contamination has occurred. The tools have been re-cleaned, tested, and returned to production (Figure 3).

The methods used for evaluating copper contamination are TXRF and VPD (vapor phase decomposition). TXRF is a technique that provides information on contaminants on semiconductor wafers. Sensitivity levels of about 1Xe10 atoms/cm2 can be achieved. The TXRF technique can be done on-site and the results are immediate. VPD, which is more accurate and has sensitivities down to the 1Xe09 atoms/cm2 has a longer turn around time and samples must be sent out for analysis.

Conclusion

It has been demonstrated that an existing high volume non-copper wafer fabrication facility can successfully incorporate a copper backend into the facility and minimize the risk of contamination. By adapting protocols that consider workflow, wafer handling hardware, fab personnel education, and tool sharing, a low cost solution to integrating copper processes has been accomplished. Continuous monitoring of the shared tools and strict enforcement of the copper protocols have been the keys to the success of the project.

Acknowledgments

The authors would like to acknowledge the following for their contributions to this work: Wilbur Catabay, Director of Research and Development and the entire Santa Clara development group for their cooperation during the relocation, Mark Ohlson, Mike Cullen, Kelly Tuter, Erika Hopper, and Robert Broyles who managed the Gresham side transfer team.

Steven Reder is a Principal Engineer at LSI Logic