The importance of contamination control in semiconductor manufacturing is well known. Through the introduction of SMIF and FOUP technology in combination with minienvironments at each process tool, major improvements were achieved in this area. In order to be prepared for future challenges, contamination has to be controlled in the complete manufacturing chain, namely the raw materials (e.g. wafers), consumables (e.g. gases, chemicals), personnel, and the semiconductor manufacturing process itself. Production of the process equipment also has to be carefully monitored and controlled. This article outlines measurement procedures and the results of a joint contamination control initiative effort to adapt the manufacturing, assembly, and testing process of leading edge immersion lithography scanners to meet future process technology requirements.

Since the 1970s we have witnessed an incredible evolution of the complexity of integrated circuits. Moore’s law, which postulates that the quantity of transistors on an integrated circuit (IC) with minimal component cost can be doubled every two years, is still valid over 34 years later. The semiconductor industry utilizes Moore’s law to coordinate future process technology developments; therefore in order to implement them, geometries on an IC have to shrink. Consequently, the immediate environment coming either directly or indirectly into contact with the wafer during the fabrication must meet an improved cleanliness specification as well. Nowadays, structures of 50 nm (DRAM ½ pitch) require a direct process environment of ISO 2.0. With the implementation of minienvironment technology, closed wafer carriers and SMIF/FOUP technology, the direct process environment is now virtually “particle free” (based on critical particle size). Further improvement was realized through the consideration of contamination control aspects during the engineering phase of process tools, but all these collective efforts will not be sufficient to be compatible with future requirements. New methods of contamination prevention are necessary; a new chapter in contamination control has to be written.

NEW CONTAMINATION CONTROL STRATEGY
Since the beginning of 2007, ASML, a lithography process tool manufacturer in the semiconductor industry, and M+W Group have been working together with the goal to improve contamination control for the production of ASML’s immersion scanners.

A joint team of experts developed a new holistic approach to improve PDT (Pattern Defect Test) and PWP (Particle per Wafer per Path) values, which are typically measured after the final test before shipment. This approach analyses and controls all contamination sources in order to optimize contamination control, not only particle sources that directly influence a wafer during production, but the whole supply chain of the immersion tool’s manufacturing and assembly itself. The whole assembly process of the scanner, including the assembly or construction process of subsystems delivered by numerous suppliers has to occur under controlled conditions.

This approach posed a challenge to both ASML for the assembly operations as well as their suppliers, although many of these operations were already being performed in state-of-the-art cleanrooms (ISO 6-7), utilizing standard cleanroom protocol procedures. Nevertheless, test data clearly indicated that further improvements were necessary to comply with ASML’s client requirements for the next technology nodes.