Speed no longer depends on feature size, but on interconnect distance.

To allow the continuation of Moore's Law, IC manufacturers have increased the power of semiconductor devices by decreasing feature size. However, the limiting factor the industry is facing when reaching 0.13 µm technology nodes and beyond is an increase in signal delays at the interconnect level. Smaller feature sizes mean increased density, closer proximity of circuit interconnects and bigger line-to-line capacitance, which results in an even greater signal delay. Interconnect delays increase with the square of the reduction in feature size whereas gate delays generally decrease linearly with the same reduction in feature size. When reaching the 0.18 µm node, the speed performance of a device no longer depends on its feature size but on interconnect distance.

The conventional approach to compensate for this increased delay is to add more layers of metal, but this increases production costs and generates more heat in the device, affecting its performance and reliability. To avoid these cost and performance problems and still allow the continuation of Moore's Law, the industry is migrating to copper instead of conventional aluminum as the interconnect metal. Copper has much greater conductivity than aluminum and is less susceptible to electro-migration, allowing the copper lines to be thinner under current load.

However, to significantly increase speed performance in next generation devices, copper must be integrated with ultra-low-k dielectrics (k< 2.5). The transition to copper alone only improves speed performance by 30% but when silicon oxide (k= 4) is replaced with ultra-low-k dielectrics an increase in speed performance can be as high as 266%. Today's low-k dielectrics strategy is a gradual migration from oxide (k= 4) to fluorinated oxide (k= 3.5) to low-k dielectrics (k< 3) and finally to ultra-low-k materials below k= 2. And since each generation of dielectric materials has different mechanical properties and characteristics, device manufacturers need to develop CMP and other related processes for each generation of dielectric material. Such a multi-step strategy is, however, very costly and high risk because of the uncertainty for the success of device manufacturability, tool and process extendibility, manufacturing yield and device reliability. An alternative to the migration strategy described above is to leap directly to ultra-low-k dielectrics below 2.2. The risk and cost of migrating to tighter design rules will be substantially lower because of the elimination of expensive development cycles for each generation of dielectric and its associated process integration challenges. Ultra-low-k dielectrics are generally porous and their k value can easily be changed by increasing the porosity without changing the actual material and process tool. However, the ultra low k dielectrics used in copper structures have insufficient adhesion and mechanical strength to survive the stress placed on them by a conventional CMP process.

Fig 1a Rupture in the line Fig 1b Delamination of low k Fig 1c Stress free polishing

The physical limitations of CMP especially for 0.13 µm manufacturing nodes and beyond have created a challenge for the IC industry in adopting low k material and aggressive design rules. Developing a viable solution for these processes integrated with ultra low k dielectrics without compromising device performance reliability yield and overall cost of ownership has become most challenging. Due to the mechanical force applied in conventional CMP, copper lines are moved back and forth during the polishing process. This results in critical damage to the interconnect structures Figure 1a, delamination of the ultra low k dielectric Figure 1b, and eventually yield loss in the current 0.13 µm process technologies making it highly unextendable for future technology nodes.