ESD CONTROLS FOR ELECTRONICS MANUFACTURING have been in place for decades, primarily in circuit board assembly. As devices have become more sensitive over time, the controls have widened in scope into semiconductor back-end operations and, in some cases, even into the front-end. While there have been improvements in materials and methods of ESD control over this period and some factories have done a better job than others in implementing them, the fundamental capability of the methods has not changed appreciably. As a result there has always been a vaguely defined lower limit of device thresholds where even good ESD programs have encountered great difficulty in handling and protecting a particular device.

In one example, a world class program at a major telecom manufacturer was brought to a virtual standstill by a 20 volt CDM device. This resulted not because the device could not be designed with built-in protection, but rather, the device designers determined that it would not be possible to achieve the desired performance. Therefore, they totally eliminated the available protection schemes and assumed that the factory controls would take care of them. The device was intended to operate at 1.7GHz which was a pioneering achievement for telephone transmission systems of the time. The challenges of dealing with Class 0 (thresholds below 200 volts) devices in standard manufacturing environments has been simmering under the surface for the decade that followed [1].

At the time, the MOS processes were using about one micron feature sizes. Further, high speed applications such as the advanced lightwave system were rare in high volume production. RF and other applications were handled in specialized, usually manual operations. What is happening today that is driving up the concern about these devices?

Today, the 90nm technology node is in place and 65nm and 45nm are not far off. The number of end applications which are poised to take full advantage of the performance capability of each succeeding generation of technology has increased many-fold. The 2003 ITRS Technology Roadmap [2] includes estimates of the maximum allowable static fields (converted to voltage units) that will be tolerated in back-end manufacturing. The data are summarized in Figure 1.

These estimates are based on the expected evolution of CMOS technology over the next decade. As such, it represents the expected behavior of the major device populations as new devices are realized in the new technologies. The result is expected to be continuing drift downward in ESD thresholds (both HBM and CDM). This is represented conceptually in Figure 2. It is expected that the vast majority of devices will have robustness to ESD similar to current designs through the continued evolution of protection strategies in each new device generation (technology node). However, the number of devices with low ESD thresholds can be expected to increase as the lower tail of the distribution curve moves downward. This is the “technology node” contribution to the increase in the number of Class 0 devices in production and assembly.

This is likely to be the smaller of the two main contributions. The other main transition in the electronics industry is the movement of very high speed and performance devices into large consumer markets. The convergence of wireless telephones, cameras, PDAs, and computers into single devices is dramatically increasing the number of devices which will be performance-limited in their ESD capability. In terms of our evolving distribution model, this means that the distribution is becoming significantly bimodal as represented in Figure 3.