New product ideas in microelectronics often are created in prototype with a solid foundation and a path to scalability. But with shrinking R&D dollars and staff, the process of bringing those ideas all the way to manufacturing often run into insurmountable hurdles. There are no shortages of IC product ideas as well as other emerging technologies, including thin film batteries, solar cells, energy scavenging, lab on chip, LED, clean technology, and more; but the path to scalability is not so clear.
With the emergence of fabless IC companies, foundries have evolved over the past 20 years into production vehicles. But as foundries have become larger and larger, their ability to run small lots, develop processes, or work with anything other than volume manufacturing runs has decreased. Small, specialty foundries, with the agility to develop processes and not just finished products, have stepped in to fill the void.
Hotbeds of R&D, the most proficient and well-known being Silicon Valley, have changed since the early 1960s. Once the strength of the Valley, company R&D labs employed the best and the brightest and from that grew a wealth of process and product knowledge. These enterprising engineers and scientists developed new products and had the infrastructure and supply chains close by to take those ideas to the manufacturing floor. Now, new companies in Silicon Valley or at other R&D outposts have similar creative ideas for products in microelectronics, but getting those products to the manufacturing floor is much more of a challenge.
In the 1980s, SEMATECH tried to fill that vacuum. Stocked with equipment and engineers, the Austin, Texas, facility tried to make U.S. IC makers competitive on a global scale. Recently, Silicon Valley Technology Center (SVTC) had a similar business model: use our equipment, develop your process, and then take that process to production. The demise of SVTC in 2012 narrowed the path to scalability of new product ideas.
From concept to product
Many new companies rely on a small team of engineers to develop a product concept. But these engineers rarely have the knowledge to take that concept into a lab environment to produce the end product ready for volume manufacturing. One reason this process between concept and production is failing is the proliferation of different products and processes.
When CMOS, memory, and other silicon-based products were being developed, there was a network of smaller companies built around bringing those processes to production. Mask shops, chemical suppliers, lithography vendors, and others in the supply chain would contribute to helping the design reach maturation. This network often had talented process engineers on staff to solve problems and offer solutions. Many silicon-based IC products had similar processes and this knowledge was shared without giving away company IP. Now process requirements are much broader, the talent pool across the R&D landscape is much smaller, and many of the unique vendors have disappeared entirely. With the business models within technology changing and the emergence of foundries as major manufacturers of multiple products for many companies, it’s now a long march to scalability.
Niche products that have unique processes and materials have heightened risk models associated with manufacturing. They often need solutions that cover everything from design through fabrication, test, and packaging. These new processes can include:
• Lithography on both sides of the substrates
• Imaging of thick photoresist films for high aspect ratio plating structures
• Processing with new materials such as piezoelectric, III-V compounds, glass, and magnetic
• New substrates that run the gamut from transparent to thin to flexible to perforated
The business models for the different methods to get a product from concept to product also vary and many have costly downsides. The university model offers a low cost solution, but typically the time to market is slow and mostly focuses on proof of concept where the IP generated is shared between the researcher, student, and professor.
Sometimes captive fabs offer these development services. In this model the company retains its IP and the effort is collaborative, but the cost is high and the time to market, although fast, may not be available at all because of limited manufacturing space at the fab.
The large foundry model offers a low initial cost for high volume projects and an intermediate time to market, but the downside includes shared IP and a very selective process to qualify for the volumes needed to manufacture. Also, small lots are typically cost prohibitive.
Many of the tools needed to take a process from concept to production are available at universities, especially in California, including UC Santa Barbara, UCLA, UC Berkeley, and Stanford. But access is only half the battle. Most development engineers and design scientists have limited training on the myriad pieces of process equipment needed to define the production process.
However, small specialty foundries partnering with universities can provide the engineering resources, processing expertise, years of experience, and equipment to help new products reach production efficiently. They can provide a method to process a product, scale it up, and produce a blueprint to take that product to a larger foundry like Globalfoundries or TSMC for volume manufacturing.
Small foundries offer flex
Many specialty foundries have built their business reputation by being flexible and diverse. They typically work with wafers from 50mm to 300mm (and now 450mm; see sidebar) of different shapes including squares and pieces. They have flexibility in the substrate materials they process including silicon but also sapphire, glass, III-V, and others. And many offer a multitude of process parameters including lithography, thin films, LPCVD, PECVD, metals, wet etches, and cleaning processes. They made their mark working with many different products and can offer ideas and suggestions to get those products to production more quickly and efficiently. Many are ISO certified, provide Class 100 cleanrooms, and have unique and tested quality tracking systems to guarantee process duplication, ready for scale up.
With an ever-increasing global demand for microelectronic products that are smaller, faster, and more powerful, design engineers and scientists must prove that a prototype concept can be manufactured cost-effectively. Many of the tried and true methods are no longer readily accessible or available. R&D staffs, supply chains, and process expertise have been stretched thin to cover the new products, substrates, and materials in demand today. Small specialty foundries are primed to fill these voids and ensure that new products do not die on the road from idea to output.
Sidebar: 450mm Wafers
As fab costs continue to escalate, IC makers have had their sights set on 450mm wafer production. It’s another roadblock that smaller, niche products must hurdle to get to volume manufacturing. 450mm wafer production enables an IC manufacturer to process twice as many die as a 300mm wafer. In comparison, a 300mm wafer is the size of a dinner plate; a 450mm wafer the size of an extra-large pizza. The more die on a wafer, the more the IC maker increases production and the lower the cost of the chips. Fabs have been using 300mm for more than a decade and for almost as long, there has been talk to move to the new size. But equipment makers have balked at developing a new class of manufacturing tools for this technology and R&D engineers have limited access to 450mm processing.
Intel has been building the industry’s first 450mm wafer fab at its Ronler Acres campus in Hillsboro, Ore. No plans have been announced when 450mm production will begin; 2018 is rumored as a possibility.
G450C is an initiative by five big chip makers—Intel, TSMC, Globalfoundries, IBM, and Samsung—partnered with New York state and CNSE (College of Nanoscale Science and Engineering) in Albany. The main goal is to develop 10nm capability on 450mm wafers in 2015 or 2016. Paul Farrar, general manager of G450C, provided an update recently on the facility. He said 25 tools will be installed in the Albany cleanroom by the end of 2013, progress has been made on notchless wafers with a 1.5mm edge exclusion zone, they have seen significant progress in wafer quality, and automation and wafer carriers are working.
SEMI, the trade organization that services the semiconductor and materials industries, has created a website, www.semi.org/450, that tracks news and insights into the 450mm transition.
Keith Best is the Director of Lithography at Noel Technologies. Best joined Noel from Simax Lithography, an engineering services company that optimized lithography equipment, where he was vice president, applications. Prior to Simax, he spent 11 years at ASML, most recently as director of application development, and also worked for LSI Logic and KLA-Tencor. With both a fab and tool background, Best has been charged with supporting and expanding Noel’s existing lithography engineering services and setting a roadmap to take lithography resolution down to 0.15 microns. www.noeltech.com
This article appeared in the February 2014 issue of Controlled Environments.